We’re looking for an experienced ASIC Verification Engineer to support our client in the telecom industry. You’ll join a collaborative team working on both new and existing ASIC projects, with a current focus on algorithm IP and architecture for next-generation telecom devices.

Your Role:

You'll be part of a team driving innovation in cutting-edge ASIC designs. Expect a mix of architecture, verification, and teamwork in a dynamic R&D environment.

Requirements:

• 5+ years of experience in ASIC verification
• Strong hands-on knowledge of UVM and SystemVerilog
• Experience with complex ASIC or large FPGA designs
• Solid background in IP block verification and multi-clock domain systems
• Proven analytical mindset and result-oriented work ethic
• Ability to work independently while thriving in team environments
• Experience with Formal Verification
• Bonus: Familiarity with C, emulation, or High-Level Synthesis (HLS)